1. Field
Exemplary embodiments of the present invention relate to a method for operating a non-volatile memory device, and more particularly, to a non-volatile memory device performing a program verification operation and a read operation.
2. Description of the Related Art
There are increasing demands for non-volatile memory devices that may perform electrical program and erase operations and retain programmed data without a refresh function which re-writes a data periodically. Among the non-volatile memory devices is a NAND-type flash memory device that may store a large amount of data because adjacent memory cells share a drain or a source by coupling a plurality of memory cells in series to form a cell string.
FIG. 1 is a circuit diagram illustrating a memory cell array of a conventional non-volatile memory device.
Referring to FIG. 1, the memory cell array includes a bit line BLn, a common source line CSL, a drain selection transistor DST, memory cells MC0 to MCn, and a source selection transistor SST. The drain selection transistor DST, the memory cells MC0 to MCn, and the source selection transistor SST are serially coupled between the bit line BLn and the common source line CSL. Although one bit line BLn is shown in the drawing, the memory cell array may include a plurality of bit lines in parallel.
A gate of the drain selection transistor DST is coupled with and controlled by a drain selection line DSL, and a gate of the source transistor SST is coupled with and controlled by a source selection line SSL. The control gates of the memory cells MC0 to MCn are coupled with and controlled by word lines WL0 to WLn, respectively.
Writing a data into each of the memory cells MC0 to MCn of the non-volatile memory device is referred to as a program operation.
Here, during a program operation, to verify whether the data is properly written in each of the memory cells MCD to MCn, a program verification operation is to be performed for a corresponding memory cell whenever a program operation is performed for each of the memory cells MC0 to MCn.
Meanwhile, an operation of reading the data from a selected memory cell after the program operation is performed for all of the memory cells MC0 to MCn is referred to as a read operation. In the read operation, the voltage level applied to the drain selection transistor DST, the source selection transistor SST, and the unselected memory cells is substantially the same as the program verification operation.
However, since program states of the unselected memory cells on one side or both sides of a selected memory cell during the read operation are different from those during the program verification operation, the use of the same voltage in the read operation and the program verification operation may lead to an error in the read operation. This will be described in detail later on by referring to FIGS. 2A to 5.
FIGS. 2A and 2B illustrate the voltage applied to the non-volatile memory device of FIG. 1 depending on an operation mode and the program state of each memory cell. FIGS. 3A and 3B illustrate a difference between the program states of the memory cells. FIG. 4 is a graph showing a variation of a current flowing through a selected memory cell of FIGS. 2A and 2B depending on an operation mode. FIG. 5 is a graph showing a threshold voltage distribution of the selected memory cell shown in FIG. 2B during a read operation. The drawings of FIGS. 2A to 5 show a case where a program operation is performed sequentially from the memory cells on the part of a source to the memory cells on the part of a drain.
Referring to FIG. 2A, a verification voltage Vverify is applied to a word line WL0 coupled with a selected memory cell MCi, and a high voltage Vread1 having a predetermined voltage level is applied to the word lines WL1 to WLn that are respectively coupled with unselected memory cells during a program verification operation. In this state, the data of the selected memory cell MCi may be read by sensing a current flowing through the selected memory cell MCi.
Referring to FIG. 2B, a read voltage Vread is applied to the word line WL0 coupled with the selected memory cell MCi, and the high voltage Vread1 having a predetermined voltage level is applied to the word lines WL1 to WLn that are respectively coupled with unselected memory cells during a read operation. In this state, the data of the selected memory cell MCi may be read by sensing a current flowing through the selected memory cell MCi.
Here, the program verification operation is performed following every program operation that is performed onto each memory cell. As described above, the program operation is performed from the memory cells in the lower part. Therefore, when a program verification operation is performed after the selected memory cell MCi of the lowermost part is programmed, for example, with ‘01’, all the unselected memory cells are in erased states, for example, as ‘11’.
On the other hand, the read operation is performed onto a memory cell selected after the program operation is performed onto all memory cells. Therefore, the selected memory cell MCi of the lowermost part is in a programmed state as ‘01’ and the unselected memory cells are also in programmed states. For example, all the unselected memory cells may be in programmed states with ‘00’.
Referring to FIGS. 3A and 3B, cell threshold voltage Vtcell is lower and drain current Id is higher when a memory cell is in an erased state (see FIG. 3A) than when a memory cell in a programmed state (see FIG. 3B). Therefore, it may be seen that when a memory cell is in an erased state (see FIG. 3A), channel resistance Rcell is low.
This signifies that the channel resistance of the unselected memory cells in the upper part of the selected memory cell MCi during the program verification operation shown in FIG. 2A is lower than the channel resistance of the unselected memory cells in the upper part of the selected memory cell MCi during the read operation shown in FIG. 2B. In short, a resistor of relatively low resistance is coupled with a drain side of the selected memory cell MCi during a program verification operation, and a resistor of relatively high resistance is coupled with a drain side of the selected memory cell MCi during a read operation.
Therefore, as shown in FIG. 4, although the same high voltage Vread1 is applied to the unselected memory cells during a program verification operation and a read operation, the current (see curve B) flowing through the selected memory cell MCi during the read operation may be greatly lower than the current (see curve A) flowing through the selected memory cell MCi during the program verification operation. This signifies that the threshold voltage distribution of the selected memory cell MCi during a read operation becomes wider than the threshold voltage distribution of the selected memory cell MCi during the program verification operation.
Referring to FIG. 5, as described above, the distribution of the threshold voltage Vth of the selected memory cell MCi during the read operation becomes wide and accordingly the threshold voltage Vth of the selected memory cell MCi may become higher than a predetermined maximal threshold voltage level. Therefore, read margin may be decreased. Decreased read margin signifies that it is difficult to accurately read the program state of the selected memory cell, which eventually brings about an error in the read operation.
To sum up, according to the prior art, channel resistance becomes different based on the program state of the unselected memory cells during a program verification operation and a read operation, and accordingly, the current flowing through the selected memory cell during the read operation becomes lower than the current flowing through the selected memory cell during the program verification operation. Thus, read margin is decreased, which may bring about an error in the read operation.